Civil Engineering Reference
In-Depth Information
Fig. 3.22
CAN bit timing
Figure
3.22
illustrates the CAN bit time divided into four parts:
• Sync segment
• Propagation segment
• Phase segment 1
• Phase segment 2
The four bit time parts are comprised of a number of smaller segments of equal
length called
time quanta
(tq). The length of each time quantum is equal to the
quantum clock time period (period = tq). The quantum clock is generated inter-
nally by dividing the incoming oscillator clock by the baud rate prescaler. The
prescaler value is passed to the BTL module through the Baud Rate Presale
(BRPR) register. The propagation segment and phase segment 1 are joined to-
gether and called 'time segment1' (TS1), while phase segment 2 is called 'time
segment2' (TS2). The number of time quanta in TS1 and TS2 vary with different
networks and are specified in the Bit Timing Register (BTR), which is passed to
the BTL module.
The Sync segment is always 1-tq long. The BTL state machine runs on the
quantum clock. During the start-of-frame (SOF) bit of every CAN frame, the state
machine is instructed by the BSP module to perform a hard sync, forcing the re-
cessive (r) to dominant edge (d) to lie in the sync segment. During the rest of the
recessive-to-dominant edges in the CAN frame, the BTL is prompted to perform
re-synchronization.
During re-synchronization, the BTL waits for a recessive-to-dominant edge. Af-
ter this is over, it calculates the time difference (number of tqs) between the edge
and the nearest sync segment. To compensate for this time difference, and to force
the sampling point to occur at the correct instant in the CAN bit time, the BTL
modifies the length of phase segment 1 or phase segment 2.
The maximum amount by which the phase segments can be modified is dictated
by the Synchronization Jump Width (SJW) parameter, which is also passed to the
BTL through the BTR. The length of the bit time of subsequent CAN bits is unaf-
fected by this process. This synchronization process corrects for propagation delays
and oscillator mismatches between the transmitting and receiving nodes. After the
controller is synchronized to the bus, the state machine waits for a time period of
TS1 and then samples the bus, generating a digital '0' or '1'. This is passed on to the
BSP module for higher level tasks.
