Civil Engineering Reference
In-Depth Information
Fig. 3.1
M_CAN block diagram
A 16-bit timer counter is available to check for timeout conditions in the han-
dling of the receive FIFOs and the Tx Event FIFO. Both the timer counter and the
time-stamp generation are clocked, via a prescaler, with multiples (1-16) of the
CAN bit time.
The configuration and control of the M_CAN module is done by the host CPU,
via the Generic Slave interface. Through this interface, the CPU also reads status
information from the CAN core, the Rx Handler, and the Tx Handler. The Generic
Slave interface may be connected to 8/16/32-bit CPUs.
The Generic Master interface is used to access the 32-bit-wide
Message RAM
(single or dual channel). The CPU also has direct access to the
Message RAM
. The
transmit buffers, the Tx Event FIFO, the dedicated receive buffers, the receive FI-
FOs, and the acceptance filter elements are stored in the
Message RAM
, outside of
the module. The partitioning of the
Message RAM
can be configured flexibly (see
Fig.
3.2
). A maximum of 1,216 (32-bit-wide) words can be used per M_CAN mod-
ule; the minimum size of the RAM is determined by the application.
Gateway (GW) configurations consisting of several M_CAN modules sharing
one
Message RAM
(see Fig.
3.3
) can easily be set up. Access conflicts between the
M_CANs and the CPU are resolved by the attached RAM Arbiter state machine. No
modifications to the M_CAN module are required for their use in a GW. It is also
possible to connect several M_CAN modules to the same CAN bus, for example, to
enlarge the number of message buffers for that channel.
The interrupt flags of the M_CAN module signal status or error conditions of
CAN core, Tx Handler, and Rx Handler. The interrupt flags may be evaluated by
polling, or they may be assigned (individually) to one of two interrupt lines that are
connected to the host CPU.
