Real-Time Analysis of Human Body Parts and Gesture-Activity Recognition in 3D - 3D Modeling and Animation: Synthesis and Analysis Techniques for the Human Body - page 158

Note that the most time-consuming parts of the algorithm are computed in
parallel by different video processors and the integration to reconstruct the 3D
model is based on the processing of parameters as opposed to pixel processing.
This feature of the algorithm makes the integration of multiple cameras more
attractive. A detailed description of multi-camera architecture is presented in the
next section.
Architectures for 3D Video Processing
In this section, we present parallel architectures for a multi-camera system. We
analyze the available data independencies for the previously mentioned 2D
example, and discuss the potential architectures to exploit the parallelism that
resulted from these independencies. Three architectures — VLIW, symmetric
parallel architecture and macro-pipeline architectures are discussed. After this,
we extend our discussion to 3D systems.
The following discussion from a hardware perspective can be applied to both
standard hardware, such as PC platform, and to application specific hardware.
For real-time video applications, the demand on computation capability can be a
rather heavy burden on general processors, or even exceed their capability. As
a result, real-time video applications usually need support from application
hardware such as DSPs on video card, video capturing device, etc. For this
reason, we focus our discussion primarily on application specific hardware,
although part of our conclusion can be extended to standard computer systems.
Instruction Level Parallelism and VLIW Architecture
In pixel-level processing stages, such as background elimination and skin area
detection stages, the operations on different pixels are independent. This
independence can be converted into different forms of parallelism such as
instruction-level parallelism, thread-level parallelism, process-level parallelism,
as well as spatial parallelism, which can be utilized by array processors.
Instruction-level parallelism takes advantages of the fact that instructions in the
execution path can be issued simultaneously under certain conditions. Since the
granularity of instructions is small, instruction-level parallelism is usually associ-
ated with fine-grained parallelism existing in a program. Thread and process-
level parallelisms are explicitly exhibited in the program as it will have more than
one execution path. Thread and process-level parallelism are associated with the
large cost of initializing and terminating threads/processes. Since in our case the