Game Development Reference
In-Depth Information
Our algorithmic pipeline clearly performs a wide range of disparate operations:
•
pixel-by-pixel operations, such as color segmentation;
•
pixel region operations, such as region identification;
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mixed operations, such as ellipse fitting; and
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non-pixel operations, such as graph matching and Hidden Markov Models.
We start with operations that are clearly signal-oriented and move steadily away
from the signal representation until the data are very far removed from a
traditional signal representation. In general, the volume of data goes down as
image processing progresses.
Hardware issues
Real-time implementation of image/video processing algorithms necessitates
data and instruction-level parallelism techniques to achieve the best perfor-
mance for several application types. In this part, we will give an overview of
some multimedia processing hardware and give a detailed description of our
testbed architecture. Besides the algorithm development, hardware design is one
of the most important issues for a real-time system. Watlington & Bove (1997)
proposed a data-flow model for parallel media processing. Davis et al. (1999)
developed a multi-perspective video system at the University of Maryland. Fritts
et al. (1999) evaluated the characteristics of multimedia applications for media
processors. Researchers also pay attention to multiprocessor architecture.
Simultaneous multi-threading is proposed by Tullsen et al. (1995). Hammond et
al. (1997) proposed single-chip multiprocessor architecture. An IMAGINE
processor is being developed at Stanford University which has explicit program-
mable communication structure (Khailany et al., 2001).
Many different image/video-processor architectures exist with their own advan-
tages and disadvantages. The selection of a processor must be based on a
number of issues, including power, cost, development tools, and performance-
related features. Texas Instruments has two DSPs (the TMS320C6201 and
C6701), using a VLIW (Very Long Instruction Word) architecture, which means
that they are able to select at compilation time instructions that can be executed
in parallel, with a maximum of eight per clock cycle. The TMS320C80 has a
MIMD (Multiple Instructions Multiple Data) architecture, and it can achieve the
performances of the C6201, although its clock frequency is much slower.
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