Biomedical Engineering Reference
In-Depth Information
of a speci
c frequency. However, there is a very simple way in which DDS generators can
be made to vary their sine output frequency without varying the clocking frequency. This
is accomplished by allowing programmability of the phase increment value
fi
∆φ
. As such,
if the output of the phase accumulator increments by
∆φ
on each incoming clock pulse, the
frequency of the output sine wave is given by
f cl
3
0
φ
o
ck
f sin e
6
The frequency resolution f r of a DDS generator is thus de
ned by the number of bits n of
the phase accumulator increment register and the clocking frequency:
fi
f c
2
lo
n
ck
f r
and the output frequency is set directly by the value W of the phase accumulator increment
register:
W
f c n lock
f sin e
2
Since wide registers, large counters, and ample ROMs are easily integrated, IC DDS gen-
erators are becoming available capable of generating sine waves into the hundreds of MHz
with incredibly high resolution.
Take, for example, the circuit presented in Figure 6.8. Here a Harris HSP45102 IC
implements the phase accumulator and sine lookup table. The phase accumulator incre-
ment register in this IC is 32 bits wide and accepts a clock frequency of up to 40 MHz. In
this way, the DDS IC is capable of providing data for the generation of sine waves as low
as 0.009 Hz and as high as 20 MHz with a resolution of 0.009 Hz! The sinusoidal signal at
the DAC's output is not in
nitely pure, since at least some distortion is introduced by the
fact that the digital samples presented to the DAC for translation are quantized in both time
and amplitude. Time quantization results from the fact that the signal can change only at
speci
fi
c time intervals dictated by the clock. Amplitude quantization results from the dis-
crete nature of the digital system itself. Samples of the in
fi
fi
nitely continuous series of a sine
are stored in ROM with
finite resolution.
Obviously, time quantization errors are reduced by using as large a lookup table as pos-
sible. In the case of the Harris HSP45102, the lookup table is 8192 samples wide. It must
be noted, however, that since the number of samples used to reconstruct the sinusoidal wave
is equal to the ratio of the clock frequency (40 MHz) and the output frequency selected,
time quantization errors get worse as the output frequency increases. Voltage quantization
errors, on the other hand, are reduced by increasing the width of the data word presented
to the DAC. Because price and complexity of a high-frequency DDS circuit increases with
the DAC's resolution, a number of hobbyist projects have been presented using only 8-bit
video DACs to gain simplicity at the expense of not taking full advantage of the HSP45102's
12-bit amplitude resolution [Craswell, 1995; Portugal, 1995].
In the DDS circuit of Figure 6.8, a 12-bit TTL-input-compatible ECL DAC takes full
advantage of IC1's data word width. High-frequency harmonics generated by aliasing are
low-passed by IC3. In more sophisticated systems, a very steep digitally tunable low-pass
fi
fi
filter is used to pass the selected fundamental frequency and reject all of the sampling
aliases. The use of an appropriate low-pass
filter) becomes criti-
cal for generating clean output at high frequencies since steps become increasingly large,
and the DAC output resembles a sine wave less and less. For example, while a 40-kHz
fi
filter (usually, an elliptic
fi
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