Biomedical Engineering Reference
In-Depth Information
frequency of 5.3 kHz. When jumper JP1 is closed, the output swing is clamped at approx-
imately
2 V by diodes D3-D8.
The unique functionality of this
fi
filter comes into action when an overload occurs. IC3
in Figure 2.36 is con
fi
gured as a window comparator. Potentiometer R19 is adjusted to
7.5 V. IC3C and IC3D
function as comparators. With no input overload, both IC3C's and IC3D's outputs are low
(i.e., close to
7.5 V. IC3B is a unity-gain inverter whose output will be at
15 V). If the input voltage rises above
7.5 V, IC3C will switch and D9
will be forward biased. If the input falls below
7.5 V, IC3D will switch and D10 will be
forward biased. D9, D10, and R19 form a wired OR gate. D11 prevents the inputs of IC4A,
IC4B, and IC4C from receiving voltages below 0 V. C9, R23, and the hysteresis of the
Schmitt action of IC4 form a one-shot that acts as a pulse stretcher, causing LED1 to illu-
minate. R24 and D12 clamp the positive voltage reaching IC5A to
8 V. IC5A and IC5B
are connected as series inverters whose outputs, labeled A and B, drive transmission gates
IC2A and IC2B. Note that A is also ANDed via D13 into IC5C (Figure 2.38).
On receipt of an input overload, IC2A will open and IC2B will close, thereby discon-
necting the high-pass
fi
filter from the overload. This action is enhanced when the low-pass
fi
filter is in the circuit (i.e., SW1 is not set to bypass) because the low-pass
fi
filter introduces
a delay to the signal. The net e
ect is that IC2A opens and IC2B closes
before
the over-
load signal has emerged at the output of the low-pass
ff
filter.
The circuit's output (marked D in Figure 2.37) is fed to the precision full-wave recti
fi
fi
er
of Figure 2.38 con
gured around IC6A and IC6B. For positive half-cycles, D14 is forward
biased and the circuit behaves like a cascaded unity noninverting ampli
fi
er. C10 ensures
stability. For negative half-cycles, IC6A and D15 form a precision half-wave recti
fi
er
whose output (at D15 anode) is fed to the unity-gain inverter formed by IC6B/R26/R28.
The net result is a fast full-wave recti
fi
fi
er that requires only two matched resistors (R26
and R28).
The output of the full-wave recti
er is fed to a comparator formed by IC6D. R30, D16,
and D17 limit the comparator output to the
fi
8 V range for application to NAND gate
IC5C. The output from IC5C is inverted by IC5D, whose output is labeled C. Under nor-
mal conditions (i.e., not output overload or input overload), C is low. If an overload occurs,
the magic of the circuit kicks in, C goes high, thereby enabling transmission gates IC2C
and IC2D. R8 and R11 are switched in parallel with R9 and R10, respectively, when IC2C
and IC2D close. The cutoff
filter of Figure 2.37 formed around
IC1C is increased to approximately 50 Hz and the output of the
ff
frequency of the high-pass
fi
fi
filter rapidly settles toward
0 V as C4 and C5 discharge.
The rest of the circuit is used to drive a TSM39168 VU LED bar graph display. The out-
put from the full-wave recti
er formed by IC6
and D18. R32, R33, and C11 form an attack/decay circuit where the attack time (i.e.,
charge time of C11) is determined predominantly by R32/C11 and the decay time by
R33/C11. The bar graph display of Figure 2.39 has an integrated driver circuit with VU
meter calibration. The scale factor is set by R33 and R34. The transition from the green
LEDs to the orange LEDs occurs at 1 V. The tenth LED (red) is activated when the volt-
age reaches 1.5 V. The output from this last LED is taken to a comparator formed by IC7A
and resistor divider R34 and R35. The comparator output feeds the one-shot formed by
D19, R36, and C13 and the Schmitt inverters IC4D, IC4E, and IC4F. The stretched pulse
illuminates LED2 to indicate that the output level is too high.
A voltage of
fi
er is fed to the precision half-wave recti
fi
15 V for the
fi
filter unit is supplied via connector J1. C15, C16, C19, and
C20 from input
fi
filters for the
15-V supply to reduce crosstalk between channels. IC8 and
IC9 are low-power
8-V regulators to supply the analog transmission gates (IC2) and the
quad NAND gate (IC5). The
5-V power for the bar graph display has a separate ground
circuit and is
fi
filtered by C23, R38, and C12 to prevent noise from being fed into the
ampli
fi
er stages.
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