Biomedical Engineering Reference
In-Depth Information
graphene
source
drain
SiO 2
n + Si (gate)
Fig. 1.31
Schematic representation of the graphene FET
Tabl e 1. 1 Characteristics of the main methods to produce graphene
Starting material
Brief description of method
Yield
Quality
Area
HOPG
Repetitive peeling
Low
Very high
Small
SiC
Reduction of Si at the surface
Medium
Medium
Wafer size
of SiC at very high temperatures
GO
GO dispersion in hydrazine
High
Medium
Large
Gas mixture (CH 4
CVD
Very high
High
Very large
and H 2 )
doping in semiconductor devices because both effects shift the Fermi energy level.
In particular, the analogues of chemical p or n doping in graphene are obtained by
applying negative or positive electrostatic gate voltages, respectively.
To implement specific devices, electrodes need to be patterned on the graphene
sheet after its deposition on the Si=SiO 2 structure. An example of such a device is
the graphene-based field-effect transistor (FET), displayed in Fig. 1.31 .
The customary method to deposit graphene on Si=SiO 2 relies on mechanical
exfoliation of highly ordered pyrolytic graphite (HOPG) using an adhesive tape,
and a subsequent release of the graphene flake on Si=SiO 2 following tape removal.
HOPG is a 3D structure consisting of vertically stacked graphene sheets. The
fragments of HOPG obtained by mechanical exfoliation, including graphene, stick
to the Si=SiO 2 surface due to van der Waals forces. This quite rudimentary method
allows the production of graphene flakes with dimensions up to 1 mm ( Geim 2009 ).
More complicated techniques to obtain and handle graphene include the AFM
microcleavage of HOPG pillars and subsequent deposition on Si=SiO 2 surfaces,
epitaxial growth of graphene, and the growth of graphene by CVD techniques. All
these graphene growth techniques were recently reviewed in Soldano et al. ( 2010 ).
Tab le 1.1 presents the characteristics of the main methods to produce graphene.
Graphene has amazing physical properties. In particular, it has ambipolar trans-
port characteristics, which can be controlled by the gate voltage in configurations
similar to that displayed in Fig. 1.31 . Moreover, the room-temperature mean-free
 
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