Cryptography Reference
In-Depth Information
100
Faults
Single errors
Multiple errors
80
60
40
20
0
1280
1270
1260
1250
1240
1230
Voltage [mV]
2
4
Fig. 17.12
Occurrence of faults in an FPGA where the S-Boxes use the
GF
(
)
representation
All the write accesses are correct, but read accesses can be faulty. This asymmetry
is caused by the heterogeneity of the CPU architecture.
17.4 Conclusion
This section mentions and details global injection techniques already studied.
•
Glitches on global lines
are described using the clock in [15] and in the power
line with the modified CLIO board produced by Gemplus Card International [21].
Glitches on the clock obviously contribute to violating the critical path, whereas
glitches on the power line increase the propagation time through the gate, thus
causing faults when the accumulated propagation time gets larger than the clock
period.
•
Overclocking
is simulated in [136, 114] and realized experimentally with an
FPGA [5, 148] and with an ASIC [353]. Overclocking is the continuous counterpart
of glitches in the clock.
•
Under-powering
is described in [23]. It also causes a slowdown of the combina-
tional logic, thus permitting setup violations.
•
Heating
can be a means to inject global faults, as discussed in [73, 169, 408]. As
exemplified by the CPU burn bench [336], errors caused by excess of heat can be
caused by an internally generated abnormally high activity.
In conclusion, all of the methods described in this section come down to the
violation of a critical path. Thus, the attacker has a wide array of methods to induce
faults, and all these threats should be considered, since a skilled attacker will naturally
use the easiest method of attack available.
