Cryptography Reference
In-Depth Information
100
Faults
Single errors
Multiple errors
90
80
70
60
50
40
30
20
10
0
760
770
780
790
800
810
820
830
Voltage [mV]
Fig. 17.7
Occurrence of faults
17.3.1.4 Experimental Results: Coverage Estimation Software Tool
In this section, a description of a fault analysis is used to find the occurrence of a
single byte fault that affects the state matrix of AES. Attention is focused on the
data path, while the key schedule is assumed here to be fault-free. This choice is
motivated by our goal to reproduce Piret and Quisquater's differential fault analysis
[397] on a smart card. This attack is detailed more thoroughly in Sect. 4.2.2 .Itis
straightforward to adapt the results obtained in this section to other attacks, such as
attacks on the key schedule [160]. The purpose of this study is to demonstrate the
effect of under-powering the device on the faults generated throughout the encryption
process.
Figure 17.7 shows the occurrence of faults for a given under-powering of the device
(this kind of characterization is identical to the one already presented Fig. 16.4 ). It
appears that within about 60 mV, the device moves from an error-free state to a fully
erroneous behavior. As already explained in Fig. 17.6 , faults are partitioned into
“single” and “multiple”, depending on whether they are covered by the “encrypt”
function for a fault f . Single faults have a distribution in a “bell shape”, where the
maximum is reached at voltage
800 mV, where 30 % of detected faults are single
bits. This behavior is compatible with a fault model where errors are caused by a
setup violation on a critical combinatorial path. The lower the power supply, the more
likely a critical path is violated, and thus the most frequent faults are single faults.
Nevertheless, below the
800 mV threshold, multiple critical paths are violated.
Hence an augmentation of multiple faults and a subsequent diminution of single
faults was observed.
 
Search WWH ::




Custom Search