Cryptography Reference
In-Depth Information
Table 17.2
Table for the rating factors of global and local fault attacks (see classification termi-
nology in [75, p. 21])
Global faults
Local faults
Factors
Identification
Exploitation
Identification
Exploitation
Elapsed time
one hour
one week
one month
one hour
Expertise
Layman
Layman
Expert
Layman
Knowledge of the TOE
†
Public
Public
Critical
Public
Access to TOE
†
10 samples
10 samples
100 samples
10 samples
Equipment
None
Standard
Specialized
Specialized
Open samples
Public
Public
Public
Public
†
TOE is short for “Target Of Evaluation”.
Caption:
Easy
Nominal
Hard
fault injection [332, 404], which induces a local voltage drop, thereby mimicking an
under-powering attack.
With regard to the common criteria (CC) international standard for computer
security certification [100], a reference for the definition of such attacks has been
agreed upon in a supplemental document [75]. It defines the difference between two
phases in an attack scenario: the identification and the exploitation. Basically, the
difference between global and local attacks is that
•
global attacks need no identification phase, but are not always successful in the
exploitation phase, whereas
•
local attacks require an extensive and methodical identification phase, but enable
an extremely fast and focused exploitation phase.
An example of the common criteria definition is given in Table
17.2
; it makes it
possible to contrast global versus local attack strengths, based on a coarse rating of
three categories: easy, nominal, hard.
17.2 Faults Model
The majority of the global faults on clocked circuits are caused by a timing constraint
violation. This section starts with a brief review of propagation delays in CMOS logic
styles. Then, timing constraint related to usage of synchronous logic are explained,
and the effect of constraints violations is analyzed. Finally, these theoretical pre-
dictions are transposed to nonCMOS logic styles, typically involved in protected
implementations.
