Cryptography Reference
In-Depth Information
15.5 Conclusion
We have presented in this chapter an evaluation of the effect that an error detection
circuit may have on the resistance to power analysis attacks on hardware implemen-
tations of cryptographic S-Boxes. The evaluation was carried out using the STMi-
croelectronics 90 nm CMOS technology library and specific synthesis and place and
route options to prevent the tool from removing the redundancy that is present due
to the added error checking circuitry.
Our results show that the presence of the error detection/correction circuit
increases the amount of information available to the attacker. We also show that,
depending on the particular attack hypothesis, the adversary may take advantage of
this additional information.
It is important, however, to mention that our conclusions regarding the impact
of the different error detection and correction codes on the vulnerability to power
analysis attacks may be different for other design environments. As is typical with
hardware designs, even the same high-level description of a module may lead to a
quite different VLSI circuit if the design options and technology library are changed.
Nevertheless, when incorporating fault detection or correction circuits into hard-
ware implementations of cryptographic algorithms, it is of crucial importance to be
aware of the possible effects that the added redundancy may have on the robustness
against power analysis attacks.
The experiments presented in this chapter provide an example of how to perform
an evaluation of the vulnerability of the designed circuit to power analysis attacks
prior to manufacturing.
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