Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks - Fault Analysis in Cryptography - page 250

S-Box with error
correction/detection
HDL code

RTL
validation

CMOS Library
front-end back-end view
synthesis
(Synopsys)

post-synth
validation

synthetized netlist

floorplan
P&R
(Encounter)

transistor models

post-P&R
validation

parasitic
(spef)

routed netlist

0101001.

test vector
(VCD format)

0101001.
1100001.
1100001.

SPICE level simulation
(Synopsys Nanosim)

i-vdd(t) Vdd current files

Fig. 15.3 The experimental setup

Table 15.1 Post Synthesis area of each error detection/correction circuit in gate equivalent (GE)

area units
S-box type Circuit area (GE)

Reference 568

Parity 698

Complemented Parity 794

Double Parity 838

Residue Modulo 3 872

Residue Modulo 7 1013

Hamming Code 847

from happening, we first synthesize each component of the circuit separately and then
connect the individual components together, forcing the tool to not further optimize
the internal design of the individual components. The number of equivalent two-input
NAND gates of each circuit is reported in Table 15.1 .