Cryptography Reference
In-Depth Information
Chapter 15
Interaction Between Fault Attack
Countermeasures and the Resistance Against
Power Analysis Attacks
Francesco Regazzoni, Luca Breveglieri, Paolo Ienne and Israel Koren
Abstract
Most of the countermeasures against fault attacks on cryptographic
systems that have been developed so far are based on the addition of information
redundancy. While these countermeasures have been evaluated with respect to their
cost (implementation overhead) and efficiency (fault coverage), little attention has
been devoted to the question of the impact their use has on the effectiveness of
other types of side-channel attacks, in particular, power analysis attacks. This chap-
ter presents an experimental study whose goal is to determine whether the added
information redundancy can increase the vulnerability of a cryptographic circuit to
power analysis attacks.
15.1 Introduction
In this chapter we discuss in a comprehensive way the interaction between coun-
termeasures against fault injection attacks and the vulnerability to power analysis
attacks, using AES as an example. We focus in particular on the non-linear trans-
formation (S-box) within AES since it is the preferred attack point. Specifically, we
concentrate on hardware implementations of AES to which error detection circuits
