Cryptography Reference
In-Depth Information
2
|i |
p
i
4i
2+4i
3+6i
1+2i
5+3i
5+i
i
2
s
|s |
p
Latch Enable
M
M
q
f(s,i)
s
R
M
M
Randomizer
2
z
|z |
p
Fig. 11.11
Time redundant (serial) arithmetic hardware implementation of the next-state logic
s
,
|
(
s
)
2
using the computed function
f
. In this computation,
all the main data path operations are conducted over modulo
M
. Also note that each
arithmetic unit (in both function
f
and the randomizer unit) is a robust one which
implements nonlinear error detection individually. For example, all the multipliers in
function
f
and the randomizer unit compute the output and its redundant checksum
using the inputs and their redundant checksums. These individual components can
detect an injected fault and raise an error signal. Next, using the randomizer unit,
we compute
z
(
s
,
i
)
, we compute
(
|
p
)
s
+
. These operations are conducted using robust
arithmetic units and are over modulo
M
as well. The resulting randomized next-state
value is then fed as the current state value into the next-state logic in the next iteration.
Note that we do not need to recover
s
for the following next state computation. Since
the function
f
=
R
×
q
(
mod
M
)
and randomizer unit work modulo
M
, the next-state value will
always be a randomized image of the correct next state value. The nonredundant
form of the next-state value (
(
s
,
i
)
GF(
q
)) can always be computed by reducing the
randomized images modulo
q
. The resulting implementation is shown in Fig.
11.11
for this specific example. For details on FSM security using nonlinear codes, the
reader is referred to [10].
∈
11.7.3 Implementation Results
In order to measure the performance of our scheme, we implemented the following
cases for the FSM, shown in Fig.
11.10
:
1. regular FSM with no error detection or any type of redundancy.
2. FSM protected with
(
,
,
)
10
5
5
co-set randomized robust codes (our solution).
