Cryptography Reference
In-Depth Information
Another architecture is presented in [123] and uses the combination of point vali-
dation and parallel computation. In this approach, two scalar multiplication modules
are used with different encodings of the point
P
and the scalar
k
using Properties
10.5 and 10.6. The outputs of the modules are compared for fault detection purposes.
Also, point verification modules are used to validate the outputs of the scalar mul-
tiplication modules. This approach has higher area overhead in comparison to the
recomputation approach.
Parallel computation and recomputing approaches are also merged in [123] to
implement another fault detection circuit. In this architecture, two scalar multiplica-
tion modules are used (i.e., parallel computation) and each module uses two differ-
ent encodings of
P
and
k
based on Properties 10.5 and 10.6 (i.e., recomputation) to
increase the fault detection capability.
In [123], it has been concluded that the recomputation, the partial recomputation
(
l
, and the parallel computation approaches have area overheads of 42.6, 42.6,
and 137.7 %, respectively, when implemented using a NIST-recommended curve over
GF
=
16
)
2
163
on a Xilinx Virtex 2000E FPGA. Also, the parallel computation with point
validation and the parallel computation with recomputing approaches have the area
overheads of 157.8 and 162.2 %, respectively.
The time overheads of these approaches, based on the number of clock cycles,
are as follows: recomputation 108 %, partial recomputation 18
(
)
.
4 %, parallel com-
putation 13
.
35 %, parallel computation with point validation 13
.
35 %, and parallel
computation with recomputation 13
.
35 % if no error is detected in the first round and
123
.
5 % otherwise. For more information, one can refer to [123].
