Biomedical Engineering Reference
In-Depth Information
Tabl e 2. 2
Progression of integrated circuit/microfluidic chips
Tabl e 2. 3
Characteristics of the second-generation DEP chip
Process
MOSIS TSMC 0.35 m gate length 2PM4 process
Pixel size
11
11m
Pixels
128
256
3:3 mm 2
Chip size
2:3
Addressing
8-bit word line decoder, 128-bit, two-phase clocked shift register for bit
lines
Transistor count
>360,000
Pixel voltage
V
D
3-5 V, DC
1:8 MHz
Operating current
30-100 mA
Fig. 2.4 The second generation of hybrid IC/microfluidic chip incorporates a CMOS integrated
circuit. This chip contains a display of 128
256 pixels, each individually addressable and 11
11m 2 in area. The entire chip is 2:3
mm 2 large. The inset shows two active pixels
producing electric fields and attracting a nearby dielectric particle
3:3
 
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