Biomedical Engineering Reference
Schematic of a single delay cell
The duty cycle is tuned by the duty cycle controller that consists of cascaded
voltage-controlled delay lines (VCDL) and AND gates (Fig. 8.5 , bottom left).
Both of its quadrature square-wave inputs, I in and Q in (frequency: ! 0 ; amplitude:
V DD /, have a 50 % duty cycle. The AND operation on I in and its delayed version
yields I o u t , whose duty cycle varies with the amount of the total delay. The same
principle applies to Q in and Q o u t . As the total delay changes from 0 to =! 0 ,the
duty cycle shifts from 50 % to 0 %.
Each voltage-controlled delay line in the duty cycle controller consists of three
voltage-controlled delay cells, and each voltage-controlled delay cell consists of
three voltage-controlled inverters in parallel (Fig. 8.6 ). Inv-1 is a standard current-
starved inverter. Its delay is not linear with control voltage V C : with V C below a
certain threshold, the delay tends toward infinity; with large V C , the delay hardly
tunes. Inv-2, a complementary current-starved inverter with a size smaller than Inv-
1, prevents the steep delay increase for small V C . Inv-3, a current-starved inverter
with V C fed after a source follower, sustains a delay reduction with increasing V C .
These combine together to yield a more linear tuning characteristics.
The digital pulse sequence generator (Fig. 8.5 , upper left) controls the MUX and
switches S1 and S2 to produce an adequate NMR excitation pulse sequence such
as the CPMG pulse sequence, an essential task in practical NMR works [ 6 ]. The