Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 69

logic [7:0] value = 0;
assign busTx.data = value;
initial
begin
busTx.rw = 1;
for (i=0; i < 32; i++)
begin
#2 busTx.addr = i;
value += 1;

end
busTx.rw = 0;
end
// Rest of the module details here

module dst ( input bit clk,
local_bus.rx busRx);
logic [7:0] local_mem [0:31];
always @(posedge clk)

if (busRx.rw)
local_mem[busRx.addr] = busRx.data;
endmodule

// In the top-level module these modules are instantiated with interface
declaration.
module local_bus_top;

logic clk = 0;
local_bus bus(clk); // the interface declaration

always #1 clk = clk;

src SRC (clk, bus.tx);
dst DST (clk, bus.rx);

initial
$monitor ($time, "\t%d %d %d %d\n", bus.rx.rw, bus.rx.addr,
bus.rx.data, DST.local_mem[bus.rx.addr]);

endmodule

data

32

8
addr

TX RX

1
rqst

1

grant

rw

clk

clk

Local Bus

Figure 2.20 Local bus interface between two modules