Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 60

2 16 test vectors. The
simulators can spend hours or even days in exhaustive testing of designs of even moderate size. The
designer therefore needs to test intelligently, choosing sample points and focusing especially on
corner cases. For mathematical computations, the overflow and saturation logic cases are corner
cases. Similarly for other designs, the inputs that test the maximum strength of the system should be
applied.

16-bit multiplier requires 2 16 inputs. For example, testing a simple 16

2.7.4.2 Random Testing

For large designs, the designer may resort to random testing. The values of inputs are randomly
generated out of a large pool of possible values. In many instances this random testing should be
biased to cover stress points and corner cases, while avoiding redundancy and invalid inputs.

2.7.4.3 Constraint-based Testing

Constraint-based testing works with random testing, whereby the randomness is constrained towork
in a defined range. In many instances, constraint testing makes use of symbolic execution of the
model to generate an input sequence.

2.7.4.4 Tests to Locate a Fault

In many design instances, the first set of input sequences and test strategies are used only to identify
faults. Based on the occurrence and type of faults, automatic test patterns are generated that localize
the fault for easy debugging.

2.7.4.5 Model Checkers

The designer can make use of models for checking designs that implement standard protocols (e.g.
interfaces). Appropriate checkers are placed in the design. The input is fed to the model as well as to
the design. When there is non-conformity the checkers fire to identify the location of the bug.

2.7.5 Transaction-level Modeling
Many levels of modeling are used in hardware design. RTL and functional-level modeling have
already been mentioned. For functional-level modeling, algorithms are implemented in tools like
MATLAB , and in many design instances a design that is functionally verified is directly converted
into RTL. However, designs are becoming more and more complex. This is especially the case for
SoC andMPSoC, wheremore andmore components are being added on a single piece of silicon. The
interworking of the processors or other components on the chip is also becoming ever more critical.
This interworking at register transfer level is very complex as it deals with bus protocols or NoC
protocols. While analyzing the interworking of these components, usually this level of detail is not
required and interworking can only be studied by observing the physical links to make complex
packet or data transactions.
Transaction-level modeling (TLM) deals with designs that have multiple components. These
components communicate with each other on some medium. At TLM, the detailed RTL
functionality of the components and RTL protocol are not important. TLM separately deals with