Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 42

in the design can be accessed using built-invariable $ time . It is a unit-less integer. The timing at any
instance in simulation can be displayed by using the $ display as shown here:

$display ($time, “ a=%d ” , a);
The programmer can insert delays in the code by placing # < number > . On encountering this
statement, the simulation halts the execution of the statement until

of time units have
passed. The control is released from that statement or block so that other processes can execute.
Synthesis tools ignore this statement in RTLVerilog code, and the statements are mostly used in test
code or to model propagation delay in combinational logic.
Another important timing control directive in Verilog is @ . This directive models event-based
control. It halts the execution of the statement until the event happens. This timing control construct
is used to model combinational logic as shown here:

< number >

always @ (a or b)
c = a^b;
Here the execution of the assignment statement always @(a or b) will happen only if a or b
changes value. These signals are listed in the sensitivity list of the block.
The time control @ is used also to model synchronous logic. The code here models a positive-
edge trigger flip-flop:

always @(posedge clk)
dout < = din;
It is important to note that, while coding at RTL, the non-blocking procedural assignment should be used
only to model synchronous logic and the blocking procedural assignment to model combinational logic.

2.6.4.5 RTL Coding Guideline: Avoid Combinational Feedback

The designer must avoid any combinational feedback in RTL coding. Figure 2.13(a) demonstrates
combinational feedback, as does the following code:

reg [15:0] acc;
always@(acc)
acc = acc + 1;

Combinational
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Combinational
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Combinational
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Combinational
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Register

Combinational
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Combinational
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(a) (b)

Figure 2.13 Combinational feedback must be voided in RTLVerilog code. (a) A logic with combina-
tional feedback. (b) The register is placed in the feedback path of a combinational logic