Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 576

1

done

1

1 start PE 1 _done 1

PE 0 _done

read-PE 2

write

PE 0 PE 1 PE 2

8 8

read

8

write-PE 0 read-PE 1 write-PE 2

8 write-PE 1

read-PE 2

8 8

8

RAM

RAM Port A/B

RAM Port A/B

Port A/B RAM

RAM

512x8
RAM

RAM

16 deep
FIFO

FIFO

FIFO

PE 1 local mem

PE 2 local mem

PE 0 local mem

Figure 13.47 KPN-based top-level design

16

11

Information
Symbols

Checks
on
rows

11

16

Checks
on
checks

Checks on columns

Figure 13.48 Block turbo encoder to code an 11 11 block to make a 16 16 coded block

Exercise 13.5

Design and code in RTL Verilog a dedicated and time-shared architecture of a digital quadrature
mixer that multiplies 16-bit I and Q samples at baseband to digitally generated 16-bit sin ( x 0 n) and
cos ( x 0 n). The time-shared design should only use one MAC unit. Truncate the output to 16-bit
numbers. Use one of the DDFS architecture covered in Chapter 12 for sine and cosine generation.

Exercise 13.6

Use systolic FFT architecture of Figure 8.14 to design 16-QAM-based 8 sub-carrier based OFDM
transmitter and receiver blocks. Write the code in RTL Verilog and test your design with Matlab
generated fixed-point implementation.

Exercise 13.7

Implement a 16-bit folded and parallel systolic AES architecture that uses the in-place indexing
technique of Sections 13.3.3.3 and 13.3.3.4, respectively.