Digital Signal Processing Reference
In-Depth Information
1
5
9
13
1
5
9
13
1
5
9
13
1
+
i-index
8
index
+
+
+
input
. . . . . . . . .
w_addr
14
By_pass_mux
Avoiding pipeline stall
addr0
8
+
SB
+
SB
8
+
SB
8
. . . . . . . . . . . . . . . . . .
+
+
+
+
+
+
+
+
R
3
R
1
R
2
R
0
rst_n
0
rst_n
1
en
0
mux sel
0
en
1
mux sel
1
3 2 1 0
3 2 1 0
Figure 13.36
Byte systolic architecture implementing AES algorithm
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