Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 35

This statement is equivalent to the following decision logic:

if(sel)
out = a;

else

out = b;

The conditional operator can also be used to infer higher order multiplexers. The code here infers a
4:1 multiplexer:

out = sel[1] ? ( sel[0] ? in3 : in2 ) : ( sel[0] ? in1 : in0 );

2.6.3.3 Concatenation and Replication Operators

Most of the operators in Verilog are the same as in other programming languages, but Verilog
provides a few that are specific to HW designs. Examples are concatenation and replication
operators, which are shown in Table 2.6.

Example 2.2

Using a concatenation operator, signals or parts of signals can be concatenated to make a new
signal. This is a very convenient and useful operator for the hardware designer, who can bring
wires from different parts of the design and tag them with a more appropriate name.
In the example in Figure 2.10, signals a[3:0] , b[2:0] , 3 ' b111 and c[2:0] are
concatenated together in the specified order to make a 13-bit signal, p .

Table 2.6 Concatenation and replication operators

Operator type Operator symbol Operation performed

Concatenation { } Concatenation

Replication {{ }} Replication

p={a[3:0], b[2:0], 3'b111, c[2:0]};

1

MSB

LSB

p

13 bits

Figure 2.10 Example of a concatenation operator