Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 546

D 0,0 D 0,1 D 0,2 D 0,3

D 1,0 D 1,1 D 1,2 D 1,3

D 2,0 D 2,1 D 2,2 D 2,3

D 3,0 D 3,1 D 3,2 D 3,3

Figure 13.25 Filling of plain text in a state matrix

(a)

S S

S 0,0 S 0,1 S 0,2 S 0,3 S 0,0 S 0,1 S 0,2 S 0,3

S 1,0 S 1,1 S 1,2 S 1,3 S 1,1 S 1,2 S 1,3 S 1,0

S 2,0 S 2,1 S 2,2 S 2,3 S 2,2 S 2,3 S 2,0 S 2,1

S 3, 3

S 3,0 S 3,1 S 3,2 S 3,3 S 3,0 S 3,1 S 3,2

(b)

C' 0,j
C' 1,j
C' 2,j
C' 3,j

02 03 01 01
01 02 03 01
01 01 02 03
03 01 01 02

C' 0,j
C' 1,j
C' 2,j
C' 3,j

=

Figure 13.26 (a) Shift row operation of AES algorithm. (b) Matrix multiplication of mixed column

operation

13.3.3.2 AES Architectures

There are a number of architectures proposed in the literature. Selection of a particular implemen-
tation of the AES algorithm primarily depends on the input data rate. A pipelined fully parallel
architecture implements all the iterations in parallel [35]. The design supports very high throughput
rate and is shown in Figure 13.27(a). Similarly a design that uses time-shared architecture
implements one round at a time. A representative layout is given in Figure 13.27(b).
There are many applications where the architecture is needed to support moderately high data
rates in a small area, as is the case with most of the wireless communication standards. An optimal
design may require further folding the AES algorithm from the one given in Figure 13.27(b). The
design. though. is originally defined for 32-bit data units but can be broken into 8- or 16-bit data
units [32, 33]. TheHWmapping then reduces the requirement on buses, registers andmemories from
32-bit to 8- or 16-bit while supporting the specified throughput. For an 8-bit design this amounts to
almost four-fold reduction in hardware.
An example of an implementation of AES in a KPN network framework is shown in Figure 13.28.
The AES processor reads plain text data froman input FIFO. The processor has an internal RAM that
is used for local storage of temporary results. The cipher data is then stored into a FIFO and a done