Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 533

PC N

lanes

. . . .

1 2

v

Switch
arbitration

1

2 PC E

flit out

v 1

PC w 2

flit in

Flit
admission
queue

v

PC p

. . . .

1 2 v

PC s

flit in flit out

Figure 13.12 Design of a router with multiple VCs for each physical channel

identification (VCid). The process of breaking a packet into flits and assigning a VCid to each flit
is given in Figure 13.13.
At the arrival of a header flit, the router runs a routing algorithm to determine the output PC on
which the switch needs to route this packet for final destination. Then the VC allocator allocates the
assigned VC for the flit on the input PC of the router.

payload overhead

Packet (112 bits)

data bits other dst src

96 8 4 4

Flitization

Flits (28 bits)

other tail vcid body vcid body vcid body vcid dst src head vcid

16 8 2 2 24 2 2 24 2 2 24 2 2 16 4 4 2 2

Assembly

Packet (112 bits)

data bits other dst src

96 8 4 4

Figure 13.13 Process of breaking a packet into a number of flits and assigning a VCid to each