Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 33

module mux (out, in1, in2, sel);
output out;
input in1, in2, sel;
wire out1, out2, sel_n;
and #5 a1(out1, in1, sel_n);
and #5 a2(out2, in2, sel);
or #5 o1(out, out1, out2);
not n1(sel_n, sel);
endmodule

out1

in1

out

sel

in2

out2

(a) (b)

Figure 2.9 (a) A gate-level design for a 2 : 1 multiplexer. (b) Gate-level implementation of a 2 : 1
multiplexer using Verilog primitives

waveforms of input and output are plotted in a Verilog simulator. These delays are ignored by
synthesis tools.

2.6.3 Dataflow Level
This level of abstraction is higher than the gate level. Expressions, operands and operators
characterize this level. Most of the operators used in dataflow modeling are common to software
programmers, but there are a few others that are specific to HW design. Operators that are used in
expressions for dataflow modeling are given in Table 2.3. At this level every expression starts with
the keyword assign . Here is a simple examplewhere two variables a and b are added to produce c :

assign c = a + b;

The value on wire c is continuously driven by the result of the arithmetic operation. This
assignment statement is also called 'continuous assignment'. In this statement the right-hand side
must be a variable of type wire , whereas the operands on the left-hand side may be of type wire or
reg .

Table 2.3 Operators for dataflow modeling

Type Operators

Arithmetic þ ¼ * / %**

Binary bitwise & &| | ^ ^ ^

Unary reduction & &| | ^ ^ þ -

Logical ! && || ¼¼ ¼¼¼ ! ¼ ! ¼¼ ¼¼ ¼¼¼

Relational < > <¼ >¼

Logical shift
Arithmetic shift > <

Conditional ?:

Concatenation { }

Replication {{}}