CORDIC-based DDFS Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 514

12.5.3 Novel Optimal Hardware Design
Yet another approach to designing optimal hardware of the CORDIC is to map the expressions in r i
into two binary constants using reverse encoding and then use four multipliers and two adders to
compute the desired results. This novel technique results in a single-stage CORDIC architecture.
The design is shown in Figure 12.19.
The inverse coding is accomplished using (12.16). The inverse coding for const1 is simply derived
as:

N 1 N 1

1 r i 2 ði þ 1 Þ ¼ 1 b i 2 i 2 M þ 2 N

ð 12 : 22 Þ

i¼Mþ i¼Mþ

In HW design, as the original b i are kept intact they are used for computing the two constants. To
cater for the 2 N term in (12.22), a 1 is appended to b as the LSB b N , and for the 2 M factor the
corresponding b M þ 1 bit is flipped and is assigned a negative weight. Then const1 is given as:

N

¼b 0 Mþ 1 2 M þ

2 b i 2 ði 1 Þ

const 1 ð 12 : 23 Þ

i¼Mþ

where b 0 Mþ 1 is the complement of bit b M þ 1 . Similarly for const2, the first r k are computed for
i ¼ M þ

1, ... , N 1 as:

rr k ¼ r i r j where k ¼ i þ j and k P

These rr k are then inverse coded using (12.22) and an equivalent value is computed similar to the
const1 computation by expression in (12.23). For N ¼ 16 and P ¼ 16, this requires computing the

cos θ

x 4

x +

table x

-

P 2 P 1

x

x

sin θ

+

y 4

M P 1

x

table y

P 2

M

const 2 N −1 N −1 − ( i + j )

∑ ∑ 2

1 − r j

i

i = M +1 j = i +1

( i + j ) ≤ P 2

N N-M

const 1

N − 1

2 − i

∑

r i

i = M +1

Figure 12.19 Optimal hardware design with single-stage implementation of the CORDIC algorithm