CORDIC-based DDFS Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 502

A simple counter-based controller is used to appropriately select the input to each CE i . TwoMSBs
of the counter are used as select line to three multiplexers. In the first four cycles, four desired angles
and associated values of x 0 and y 0 are input to CE 0 . All subsequent cycles feed the values fromCE 3 to
R 0 to CE 0 . The successive working of the algorithm for the initial few cycles is elaborated in the
timing diagram of Figure 12.14.
The architecture works in lock step calculating N iterations for every input angle, and produces
cos di and sin di for i ¼ 0, ... , 3 in four consecutive cycles after the 16th cycle.

12.4.6 Modified CORDIC Algorithm
An algorithm selected for functional simulation in software often poses serious a limitation in
achieving HW-specific design objectives. The basic CORDIC algorithm described in Section 12.4.1
is a good example of this limitation. The designer in these cases should explore other HW affine
algorithmic options for implementing the same functionality. For the CORDIC algorithm, a
modified version is an option of choice that eliminates limitations in exploring parallel and
time-shared architecture.
The CORDIC algorithm of Section 12.4.1 requires computation of s i and only then it condition-

ally adds or subtracts one of the operands while implementing (12.14). This conditional logic
restricts the HW design to exploit inherent parallelism in the algorithm. A simple modification can
eliminate this restriction and efficient parallel architectures can be realized.
The standard CORDIC algorithm assumes as a summation of N positive or negative micro-

rotations of angles D i as given by (12.14). A binary representation of a positive value of as below

can also be considered for micro rotations:

N 1

0 b i 2 i for

¼ b i 2f 0 ; 1 g ð 12 : 15 Þ

i¼

where each term in the summation requires either a positive rotation equal to 2 i or no rotation,
depending on the value of the bit b i at location i. This representation cannot be directly used in HWas
the constant k of (12.13) becomes data dependent. A modification in the binary representation of

of (12.15) is thus required that makes values of k data independent.
This independence can be accomplished by recoding the expression in (12.15) to only use þ 1or

1. This recoding of the binary representation is explained next.

12.4.7 Recoding of Binary Representation as 1

An N-bit unsigned number b in Q1.(N-1) format can be represented as:

N 1

0 b i 2 i where b i 2f 0 ; 1 g

b ¼

i¼

The bits b i in the expression can be recoded to r i 2þ 1 ; 1 f g as :

N 1 N 1

0 b i 2 i ¼ 0 r i 2 iþ 1

ð Þ

2 0 2 N b ¼ þ ð 12 : 16 Þ

i¼ i¼

r i ¼ 2 b i 1 where r i 2fþ 1 ; 1 g