Digital Signal Processing Reference
In-Depth Information
N
x
N
y
N
K
M
M
x
N
y
N
K
x
i
M
M
M
x
i
M
x
i+1
rst_n
N
x
i+2
rst_n
0
0
x
i+1
M
M
CE
i
CE
i+1
CE
i
y
i
M
y
i
M
y
i+1
y
i+2
M
M
θ
y
i+1
i+1
rst_n
θ
rst_n
θ
i+2
d
N
θ
N
θ
i+1
θ
i
d
N
{counter , 1'b0}
θ
i
N
∆θ
i
∆θ
tan
-1
2
-i
ROM
tan
-1
2
-(i+1)
ROM
i+
addr i
4
N
1
4
1
4
even index
odd index
counter
rst_n
addr
valid
clk
tan
-1
2
-i
ROM
N
∆θ
{counter, 1'b0}+1
i
4
4
1
valid
counter
rst_n
(a)
(b)
Figure 12.12
Folded CORDIC architecture. (a) Folding factor of 16. (b) Folding factor of 8
MATLAB
and Verilog, respectively, the third column shows the difference in the results. Similarly
the last three columns are the same set of values for sin
.
12.4.4 Time-shared Architecture
The CORDIC algorithm is very regular and a folded architecture can be easily crafted. Depending on
the number of cycles available for computing the sine and cosine values, the CORDIC algorithm can
be folded by any folding factor. For N
16, the architecture in Figure 12.12(a) is folded by a folding
factor of 16. Similarly Figure 12.13(b) shows a folded architecture by folding factor of 8. The valid
signal is asserted after the design computes the N iterations. The RTLVerilog for a folding factor of
16 is given here:
¼
module CORDIC_Shared #(parameter M = 22, N = 16, LOGN = 4, K=22'h0DBD96)
// In Q2.20 format, value of K = 0.8588 K=22'h0DBD96)
(
input signed [N - 1:0] theta_d,
input clk,
input rst_n,
output reg signed [M - 1:0] cos_theta,
output reg signed [M - 1:0] sin_theta);
reg signed [M-1:0] x_reg;
reg signed [M-1:0] y_reg;
reg signed [N-1:0] theta_reg;
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