CORDIC-based DDFS Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 483

12

CORDIC-based DDFS
Architectures

12.1 Introduction
This chapter considers the hardware mapping of an algorithm to demonstrate application of the
techniques outlined in this topic. Requirement specifications include requisite sampling rate and
circuit clock. A folding order is established from the sampling rate and circuit clock. To demonstrate
different solutions for HW mapping, these requirements are varied and a set of architectures is
designed for these different requirements.
The chapter explores architectures for the digital design of a direct digital frequency synthesizer
(DDFS). This generates sine and cosine waveforms. The DDFS is based on a CoORDinate DIgital
Computer (CORDIC) algorithm. The algorithm, through successive rotations of a unit vector,
computes sine and cosine of an input angle

. Each rotation is implemented by a CORDIC element
(CE). An accumulator in the DDFS keeps computing the next angle for the CORDIC to compute the
sine and cosine values. An offset to the accumulator in relation with the circuit clock controls the
frequency of the waveforms produced.
After describing the algorithm and its implementation in MATLAB , the chapter covers design
techniques that can be applied to implement a DDFS in hardware. The selection is based on the
system requirements. First, a fully dedicated architecture (FDA) is given that puts all the CEs in
cascade. Pipelining is employed to get better performance. This architecture computes new sine and
cosine values in each cycle. If more circuit clock cycles are available for this computation then a
time-shared architecture is more attractive, so the chapter considers time-shared or folding
architectures. The folding factor defines the number of CEs in the design. The folded architecture
is also pipelined to give better timings.
Several novel architectures have been proposed in the literature. The chapter gives some alternate
architecture designs for the CORDIC. A distributed ROM-based CORDIC uses read-only memory
for initial iterations. Similarly, a collapsed CORDIC uses look-ahead transformation to merge
several iterations to optimize the CORDIC design.
The chapter also presents a novel design that uses a single iteration to compute the values of sine
and cosine, to demonstrate the extent to which a designer can creatively optimize a design.