Digital Signal Processing Reference
In-Depth Information
TDL ¼
*
arA
0
jjCR ¼
*
arB
1
þþjjCONV
The instruction saves the 32-bit of data from the address pointed by arA0 in Tap Delay Line by
storing the two 16-bit samples in TDR0 and TDR1 while respectively shifting the older values into
TDR2 and TDR3. The instruction also decrements the address stored in the address register for
accessing the new samples in the next iteration. Similarly, the coefficients stored at address pointed
by arB1 are also read in coefficient registers CR0 and CR1 while the address register is incremented
by 1. The datapath in the same cycle performs four MAC operations:
*
arX þþ=
½
¼ ACCs
where
X 2fA; Bg
The 16-bit values in two accumulators ACC0 and ACC1 are stored in memory location pointed by
arX
register.
Example: The MAC units along with special registers are configured for adaptive filter specific
instructions. The MAC units can perform four MAC operations to simultaneously compute two
output samples.
y
n
¼ x
n
h
0
þ x
n
1
h
1
þ x
n
2
h
2
þ x
n
3
h
3
þ ... þ x
nðN
1
Þ
h
N
1
y
n
1
¼ x
n
1
h
0
þ x
n
2
h
1
þ x
n
3
h
2
þ x
n
4
h
3
þ ... þ x
nðN
2
Þ
h
N
1
x
n
3
are loaded
in the
TDL
while
h
0
and
h
1
are loaded in
CR
s. The length of the filter is 40. The convolution
operation is performed in a loop
The values of
x
n
and
x
n
1
are loaded first in the
TDL
and subsequently
x
n
2
and
N=
2 number of times to compute the two samples, use circular
addressing.
arA
0
¼ xBf%
128
; ==
pointarA0tothecurrentsamples
;
use circular addressing
arB
0
¼ hbf ;
arA
1
¼ yBf
%128
accs ¼
0
x
00008000
; ==
reset the two acculators for rounding
TDR ¼arA
0
%
==
load
x½n
and
x½n
1
in TDR0 and TDR1
TDR ¼arA
0
%
==
load
x½n
2
and
x½n
3
while shifting old values
repeatc
20
==
repeat the next instruction 20 times
TDR ¼arA
0
jjCR ¼arB
0
þ þjjCONV
arA
1
¼ ACCs
11.6.3.6 Instruction Encoding
Though the instruction can be encoded in a way that saves complex decoding but in this design
a simple coding technique is used to avoid complexity. The accelerator supports both regular and
special instructions (Figure 11.14). The regular instructions are a set of orthogonal instructions that
are identical for both the data paths andAGUs. A0 at bit location 0 identifies that the sub-instructions
in the current instruction packet are orthogonal and a 1 at the bit location specifies that this is a special
or non orthogonal instruction.
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