Micro-programmed Adaptive Filtering Applications - Digital Design of Signal Processing Systems: A Practical Approach - page 468

R i ¼ R i OP R j ; where OP 2f & ; j; ^; ; þ ; g; R 2fA; Bg and i; jf 0 ; 1 ; 2 ; ...; 7 g

The accelerator can perform two parallel ALU operations on two sets of 16-bit operands from
consecutive registers:

R i ¼ R i OP R j jjR i þ 1 ¼ R i þ 1 OP R j þ 1 ;
where OP 2f & ; j; ^; ; þ ; g; R 2fA; Bg and i; j 2f 0 ; 2 ; 4 ; 6 g:

The k symbol signifies that the operations are performed in parallel.

Status Register
Two of the status register bits are used to support conditional instructions. These bits are set after
the accelerator executes a single arithmetic or logic operation on two operands. These bits are Z and
N for zero and negative flags, respectively. Beside these bits, two bits V 0 and V 1 for overflow are also
provided for the two respective MAC blocks. One bit for each block shows whether the result of
arithmetic operation in the block or its corresponding ACC i has resulted in an overflow condition.

11.6.2.3 Address Generation Unit

The accelerator has two AGUs. Each has four registers arXi (i ¼ 0 ... 3) and X 2 {A, B}, and each
register is 12 bits wide. Each AGU is also equipped with an adder/subtractor for incrementing and
decrementing addresses and adding an offset to an address. The AGU can be loaded with an
immediate value as address. The AGU supports indirect addressing with pre- and post- increment
and decrement. The value of the address register can also be stored back in respective memory
blocks. The RTL design of the AGU for addressing memory block A is shown in Figure 11.10.

size_x

0 OFFSET

1

cirA_sel ~size_x

in c_sel

arA0

arA_en

12

arA1 12

arA_en

+/-

post_inc_aadr

arA2

pre_inc_addr

arA3

0 1

pre_sel

arA_sel

0 1

arAread_sel

arA_cir_sel

memA_add_bus

0

post_inc_addr

1

0

immediate memA_data_ bus

2

1

regfileA

arA_sel

wr_mem_sel

Figure 11.10 Address generation unit A