Digital Signal Processing Reference
In-Depth Information
acc_0,acc_1
acc_0,acc_1
addr_B
addr_A
32
32
12
12
AGU
A
mem
A
mem
B
AGU
B
D
a
D
a
12
12
32
32
32
32
32
32
32
{a
a
c1,acc0}
32
{aac1,ac
c0}
regfile
A
regfile
B
16
16
A
U
A
U
16
16
i
m
i
m
16
16
16
16
16
CR
1
CR
0
TDR
0
TDR
1
TDR
2
TDR
3
16
Logic
MAC_BLK
0
MAC_BLK
1
acc1
16
16
16
acc0
Logic out
inst
Status
N
Z
V
0
V
1
Figure 11.8 Datapath of the multi-channel line echo canceller
Register Files
The datapath has two 16-bit register files, A and B, with 8 registers each. Each register file has one
read port to read 32-bit aligned data from two adjacent registers R
i
and R
i
þ
1
(i
¼
0, 2, 4, 6), where
R
2
{A, B}, or 16-bit data from memory in any of the registers in the file. The 32-bit aligned data
from memory mem_R[31:0] can be written in the register files at two consecutive registers. A
cross-path enables copying of the contents of two aligned registers from one register file to the
other. The accelerator also supports writing a 16-bit result from ALU operations to any register, or
ACC
0
and ACC
1
in two consecutive registers. A 16-bit immediate value can also be written in any
one of the registers. A register transfer level (RTL) design of one of the register files is given in
Figure 11.9.
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