Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 448

16 16

1

WRITE_1
WRITE_2

ERROR

1

FIFO

1

DEL_1
DEL_2

1

CLK

Figure 10.27 FIFO top-level design for exercise 10.3

IN_BUS_1 and IN_BUS_2 to the tail of the queue in registers R 0 and R 1 , respectively, and
appropriately adjusts already stored values in these registers to maintain the FIFO order. Similarly, a
DEL_1 deletes one value and DEL_2 deletes two values from the head of the queue, and brings the
next first-in values to OUT_BUS_1 and OUT_BUS_2 . Only one of the input signals signal should
be asserted at any point. List all erroneous/invalid requests and generate an error signal for
these requests.

1. Design an ASM chart to list functionality of the FSM.
2. Design the datapath and the micro-program-based controller for the design problem. Write the
micro-codes for the design problem. Draw the RTL diagram of the datapath showing all the
signals.
3. Code the design in RTLVerilog. Hierarchically break the top-level design into two main parts,
datapath and controller.
4. Write a stimulus and test the design for the following sequence of inputs:

IN_BUS_1 IN_BUS_2 WRITE_1 WRITE_2 DEL_1 DEL_2

0 0 0 0 1 0

10 20 0 1 0 0

30 29 1 0 0 0

- -

0 0 1 0

-

10 1 00 0

- -

0 0 0 1

- -

0 1 1 0

Exercise 10.4

Design a micro-coded state machine for an instruction dispatcher that reads a 32-bit word from
the instruction memory. The instructions are arranged in two 32-bit registers, IR 0 and IR 1 . The first
bit of the instruction depicts whether the instruction is 8-bit, 16-bit or 32-bit. The two instruction
registers always keep the current instruction in IR 1 , while the LSB of the instruction is moved to the
LSB of IR 1 .