Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 444

γ γ

odd odd

+ +

-1/2 1/2

-1/2 1/2

x[n]

x[n]

z -1

z -1

split merge

z z

1/4

-1/4

1/4 -1/4

+ +

even even

λλ

Figure 10.24 5/3 wavelet transform based on the lifting scheme

decomposed under the lifting scheme. Figure 10.24 shows an example of a 5/3 filter transformed as a
lifting wavelet; this wavelet is good for image compression applications. Similarly, there is a
family of lifting wavelets [12] that are more suitable for other applications, such as the 9/7
wavelet transform which is effective for image fusion applications (images of the same scene are
taken from multiple cameras and then fused to one image for more accurate and reliable
description) [14].
It is desired to design a programmable processor that can implement any such wavelet along with
processing other signal processing functions. This requires the programmable processor to imple-
ment filters with different coefficients. For multimedia applications, multiple frames of images need
to be processed every second. This requires several programmable processing elements (PEs) in
architecture with shared and local memories placed in a configuration that enables scalability in
inter-PE communications. This is especially so in video where multi-level pyramid-based wavelet
transformations are performed on each frame. The coefficients of each lifting filter can be easily
represented in 11 bits and an image pixel is represented in 8 bits. Themultiplication results in a 19-bit
number that can be scaled to either 8 or 16 bits. The register file of the PE is 16 bits wide for storing
the temporary results. The final results are stored in memory as 8-bit numbers.
The instruction set of the PE is designed to implement any type of wavelet filtering as lifting
transforms and similar signal processing algorithms. A representative architecture of the PE is given
in Figure 10.25. The PE supports the following arithmetic instruction on a register file with 32-bit 16
registers:

Ri ¼ Rj
Ri L ¼ Rj L OP Rk L
Ri H ¼ Rj H OP Rk H
Ri ¼ Rj OP Rk
Ri L ¼ Ri H
Ri H ¼ Ri L
Ri ¼ Rj L Rk L
Ri ¼ Rj L Rk H
Ri ¼ Rj H Rk H

OP 2f ; þ ; ; ; & ; j ; ^g
for i ; j ; k 2f 01 2 15 g

; ; ...;

Based on the arithmetic instruction, the PE sets the following overflow, zero and negative flags for
use in the conditional instructions:

Flags: OV, Z,N