Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 435

1

N

+

addr
bus

load

Micro program
Memory

N

2

M

next
addr
sel

1

0

data bus

cond_0
cond_1

2

cntr
signals

Cond
sel

next addr
sel

parity
bit

branch
addr

1

2

To data path

1

N

1

From data path

1

Figure 10.14 Micro-programmed state machine with subroutine support

The state machine, after executing the sequence of operations in the subroutine, needs to return to
the next micro-code instruction. This requires storing of a return address in a register. This is easily
accomplished in the cycle in which the call to the subroutine is made; micro_PC has the address of
the next instruction, so this address is the subroutine return address. The state machine saves the
contents of micro_PC in a special register called the subroutine return address (SRA) register.
Figure 10.14 shows an example.
While executing the micro-code for the subroutine call, the next-address select logic generates a
write enable signal to the SRA register. For returning from the subroutine, a return micro-code is
added in the instruction-set of the state machine. While executing the return micro-code, the next-
address select logic directs the next address multiplexer to select the address stored in the SRA
register. The micro-code at the return address is read for execution. In the next clock cycle the micro-
PC stores an incremented value of the next address, and a sequence of micro-codes is executed from
there on.

10.5 Nested Subroutine Support

There are design instances where a call to a subroutine is made from an already called subroutine, as
shown in Figure 10.15. This necessitates saving more than one return address in a last-in first-out
(LIFO) stack. The depth of the stack depends on the level of nesting to be supported. A stack
management controller maintains the top and bottom of the stack. To support J levels of nesting the
LIFO stack needs J registers.
There are several options for designing the subroutine return address stack. A simple design of a
LIFO is shown in Figure 10.16. Four registers are placed in the LIFO to support four nested
subroutine calls. This LIFO is designed for a micro-program memory with a 10-bit address bus.