Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 423

addr

5

input 9

PM

2 6

data cntr

4

4 next state

current state

rst_n

Figure 10.2 Hypothetical micro-programmed state machine design

replace the hardwired FSM. The designer evaluates all possible state transitions based on
inputs and the current state and tabulates the outputs and next states as micro-coding for PM.
These values are placed in the PM such that the inputs and the current state provide the index or
address to the PM. Figure 10.2 shows the design of this micro-programmed state machine.
Mapping this configuration on the example under consideration makes the micro-program PM
address bus 6 bits wide and its data bus 9 bits wide. The 2-bit input constitutes the two least
significant bits (LSBs) of the address bus, addr[1:0] , whereas the current state forms the rest of
the four most significant bits (MSBs) of the address bus, addr[5:2] . The contents of the memory
are worked out from the ASM chart to produce desired output control signals and the next state for
the state machine. The ASM chart for this example is not given here as the focus is more on
discussing the main components of the design.
The five LSBs of the data bus, data[4:0] , are allocated for the outputs cntr[4:0] , and the
four MSBs of the data bus, data[8:5] , are used for the next state. At every positive edge of
the clock the state register latches the value of the next state to the state register. This value becomes
the current state in the next clock cycle.
Example: This example designs a state machine that implements the four 1s detection
problem of Chapter 9, where the same was realized as hardwired Mealy and Moore state machines.
The ASM chart for the Mealy machine implementation is given in Figure 10.3(a). This design has
1-bit input and 1-bit output and its state register is 2 bits wide. The PM-based micro-coded design
requires a 3-bit address bus and a 3-bit data bus. The address bus requires the PM to be 2 3

¼ 8 bits
deep. The contents of thememory can be easily filled following theASMchart of Figure 10.3(a). The
address 3 0 b000 defines the current state of S0 and the input 1 0 b0. The next state and output for this
current state and input can be read from the ASMchart. The chart shows that in state S0, if the input is
0 then the output is also 0 and the next state remains S0. Therefore the content of memory at address
3 0 b000 is filled with 3 0 b000. The LSB of the data bus is output and the rest of the 2 bits defines the
next state. Similarly the next address of 3 0 b001 defines the current state to be S0 and the input as 1.
The ASMchart shows that in state S0, if input is 1 the next state is S1 and output is 0. The contents of
the PM at address 3 0 b001 is filled with 3 0 b010. Similarly for each address, the current state and the
input is parsed and the values of next state and output are read from the ASM chart. The contents of
PMare accordingly filled. The PM for the four 1s detected problem is given in Figure 10.3(b) and the
RTL Verilog of the design is listed here: