Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 413

Global Clock Buffers
(BUFGs)

Clock Region

32

10

One clock region with 20 CLBs
hight and half FPGA width

12 Clock Region

Figure 9.21 Virtex-5 with 32 global cock buffers with 10 clock regions and several CLBs in each region

distribution network will remain. To save this power, each clock buffer BUFGCE also comes with
an enabling signal, as shown in Figure 9.22(b). This signal can also be disabled internally to kill the
clock being fed to the clock distribution network. The methodology for using the clock enabling
signal of flip-flops in a slice for clock gating is given in [24].

9.7.3 FSM Decomposition

FSMdecomposition is a techniquewhereby an FSMis optimally partitioned intomultiple sub-FSMs
in such a way that the state machine remains OFF in most of the sub-FSMs for a considerable time.

CarryOUT CarryOUT

Gated
Clock CE CE CE CE

CLB

SLICE

clk

BUFGCE

FF
CE

6- LUT

CE

SLICE (1)

clk Enable

CE CE CE CE

6- LUT

FF
CE

Switch
Matrix

FF
CE

6- LUT

SLICE (0)

BUFG CE CE CE CE

FF
CE

6- LUT

CarryIN CarryIN

clock clock enable

(a) (b)

Figure 9.22 Clock gating inVirtex-5 FPGA. (a) CLBwith two slices and a slicewith four LUTs and four
FFs with clock enable signal. (b) Gating the clocks to FFs