Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 405

end
end

S4:
begin
if (IR1_L[0]) // instruction type: long

begin
read=1'b1;
next_state = S4;
IR0_L_en = 1'b1; IR0_H_en = 1'b0;
mux_sel_IRO_L = 2'd1; // move dataH -> IR0_L

IR1_L_en = 1'b1; IR1_H_en = 1'b1;
mux_sel_IR1_H = 2'd1; // move dataL -> IR1_H

mux_sel_IR1_L = 1'b1; // move IR0_L -> IR1_L

end
else // instruction type: short

begin
read = 1'b1; // no read

next_state = S5;
IR0_L_en = 1'b1; IR0_H_en = 1'b1; // load 32 bit data from PM into

the IR0 register
mux_sel_IRO_L = 2'd2;
IR1_L_en = 1'b1; IR1_H_en = 1'b1; // move IR0_L -> IR1_H and

IR1_H -> IR1_L
mux_sel_IR1_H = 2'd2;
mux_sel_IR1_L = 1'b0;

end
end

S5:
begin
if (IR1_L[0]) // instruction type: long

begin
read=1'b1;
next_state = S2;
IR0_L_en = 1'b1; IR0_H_en = 1'b1;

// load 32 bit data from PM into

the IR0 register
mux_sel_IRO_L = 2'd2;
IR1_L_en = 1'b1; IR1_H_en = 1'b1; // load the contents of IR0

in IR1 (full 32bits)
mux_sel_IR1_H = 2'd0;
mux_sel_IR1_L = 1'b1;
end

else // instruction type: short

begin
read=1'b0;
next_state = S3;
IR0_L_en = 1'b1; IR0_H_en = 1'b0; // move IR0_H -> IR0_L ;

mux_sel_IRO_L = 2'd0;
IR1_L_en = 1'b1; IR1_H_en = 1'b1; // move IR0_L -> IR1_H and