Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 402

fifo_in

Write

out_sel

D elet e Datapath

Controller

write_en

R 0

Error

0 R 1

1

R 2

2

3

R 3

fifo_out

clk

Figure 9.15 Four-entry FIFO queue with four registers and a multiplexer in the datapath

contents of IR 0 are shifted to IR 1 . The FSM remains in state S 2 . On the other hand, if the FSM is in
state S 2 and the current instruction is of type short (IS), then the instruction is dispatched to the
Instruction Decoder Short (IDS) and the FSM transition into S 3 without performing any read
operation.
4. In state S 3 , the FSM readjusts data. IR 1H representing 16 MSBs of register IR 1 is moved to IR 1L
that depicts 16 LSBs of the instruction register IR 1 . In the same sequence of operations, IR 0H and
IR 0L are moved to IR 0L and IR 1L , respectively. In state S 3 , the FSM checks the instruction type.
If the instruction is of type long the FSM transitions to state S 4 ; otherwise if the instruction is of
type short the FSM transitions to S 5 .In both cases FSM initiates a new read from PM.
5. The behavior of the FSM in states S 4 and S 5 is given in Figure 9.17(a). To summarize, the FSM
adjusts the data in the instruction registers such that the LSBof the current instruction is in the LSB
of IR 1 and the dispatcher brings the new 32-bit data from PM in IR 0 if required. Figure 9.17(b)
shows the associated architecture for readjusting the contents of instruction registers. The control
signals to multiplexers are generated to bring the right inputs to the four registers IR 0H , IR 0L , IR 1H
and IR 1L for latching in the next clock edge.

The RTL Verilog code of the dispatcher is given here:

// Variable length instruction dispatcher
moduleVariableInstructionLengthDispatcher(inputclk,rst_n,output [31:0]IR1);

reg [31:0] program_mem [0:255];
reg [7:0] PC; // program counter for memory (physical reg)

wire [15:0] data_H; // contains 16 MSBs of data from program memory

wire [15:0] data_L; // contains 16 LSBs of data from program_mem

reg [5:0] next_state, current_state;

reg read;

reg IR0_L_en, IR0_H_en; // write enable for IR0 regsiter

reg [1:0] mux_sel_IRO_L;

reg IR1_L_en, IR1_H_en; // write enable for IR1 register