Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 399

TheASM is very descriptive and provides amechanismfor a systematic and step-by-step design
of synchronous circuits. Once defined it can be easily translated into RTL Verilog code. Many
off-the-shelf tools are available that directly convert an ASM representation into RTL Verilog
code [11].
Example: Consider the design of Figure 9.9. The FSM implements counting of four 1s on a serial
interface using Mealy or Moore machines. This example describes the FSM using ASM represen-
tation. Figure 9.14 shows the representations. The Moore machine requires an additional state.
9.4.2 Example: Design of a Four-entry FIFO
Figure 9.15 shows the datapath and control unit for a 4-entry FIFOqueue. The inputs to the controller
are two operations, Write and Del . The former moves data from the fifo_in to the tail of the
FIFO queue, and the latter deletes the head of the queue. The head of the queue is always available at
fifo_out . A write into a full queue or deletion from an empty queue causes an error condition.
Assertion of Write and Del at the same time also causes an error condition.
The datapath consists of four registers, R 0 , R 1 , R 2 and R 3 , and a multiplexer to select the head of
the queue. The input to the FIFO is stored in R 0 when the write_en is asserted. The write_en
also moves the other entries in the queue down by one position. With every new write and delete in
the queue, the controller needs to select the head of the queue from its new location using an
out_sel signal to the multiplexer. The FSM controller for the datapath is described using an ASM
chart in Figure 9.16.
The initial state of FSM is S 0 and it identifies the status of the queue as empty. Any Del request to
an empty queue will cause an error condition, as shown in the ASM chart. On a Write request the
controller asserts a write_en signal and the value at fifo_in is latched in register R 0 . The
controller also selects R 0 at the output by assigning value 3 0 b00 to out_sel .Ona Write request
the controller also transitions to state S 1 . When the FSM is in S 1 a Del takes the FSMback to S 0 and a
Write takes it to S 2 . Similarly, another Write in state S 2 transitions the FSM to S 3 . In this state,
another Write generates an error as the FIFO is now completely filled. In every state, Write and
Del at the same time generates an error.
Partial RTLVerilog code of the datapath and the FSM is given below. The code only implements
state S 0 . All the other states can be easily coded by following the ASM chart of Figure 9.16.
// Combinational part only for S0 and default state is given
always @(*)
begin
next_state=0;
case(current_state)
`S0:
begin
if(!Del&& Write)
begin
next_state = `S1;
write_en = 1'b1;
Error= 1'b0;
out_sel = 0;
end
else if(Del)
begin