Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 387

x n

h 0

h 1

1

clk s

+

h N-1

sel

x n-(N-1)

clk c

rst_n

PPG &
Reduction

clk c

clk c

clk s

CPA

clk s

y n

Figure 9.5 Time-shared N-coefficient FIR filter

ROM, or registers may also be used if the design is required to work for adaptive or changed
coefficients. A new input is sampled in register x_n of the tap delay line of the design, and acc s and
acc c are reset. The design computes one output sample in N clock cycles. After N clock cycles, a
new input is sampled in the tap delay line and partial accumulator registers are saved in intermediate
registers clocked at f s . The registers are initialized in the same cycle for execution of the next
iteration. A CPA working at slower clock f s adds the sum of partial results in the intermediate
registers and produces y n .
The HW design assumes that the sampling clock is synchronously derived from the circuit clock.
The shift registers storing the current and previous input samples are clocked using the sampling
clock clk s , and so is the final output register. At every positive edge of the sampling clock, each
register stores a new value previously stored in the register located above it, with the register at the
top storing the new input sample. The datapath executes computation on the circuit clock clk c ,
which is N times faster than the sampling clock. The top-level design consisting of datapath and
controller is depicted in Figure 9.6. The controller clears the partial sumand carry registers and starts
generating the select signals sel_h and sel_x for the two multiplexers, starting from 0 and then
incrementing by 1 at every positive edge of clk c . At the Nth clock cycle the final output is generated,
and the controller restarts again to process a new input sample.