Unfolding and Folding of Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 375

1

0
1
2

y [n]

x [n]

X in

H a

0
1
2

+

2

5

4

a

b
0
a

0
1
2

x

H M

3

0
1
2

0

b

(a) (b)

Figure 8.18 Second-order IIR system. (a) Dataflow graph of the system. (b) Folded design with folding
factor 3

Example: A DFG of second order IIR filter is given in Figure 8.18(a) with three addition nodes 1, 4
and 5, and two multiplication nodes 2 and 3. Fold the architecture by a folding factor of 3 with the
folding set for the adder S a ¼

{3,_,2}. The
number of registers for each edge in the folded architecture using the equation for the folding
transformation assuming no pipeline stage in multiplier and adder, is as follows:

{4, 5, 1} and the folding set for the multiplier as S m ¼

F ij ¼ N W ij þ v j u i
F 12 ¼ 3

F 13 ¼ 3 2 þ 0 2 ¼ 4
F 24 ¼

3 þ 2 2 ¼

1
F 14 ¼ 3 þ 0 2 ¼ 1
F 45 ¼ 0 þ 1 0 ¼ 1
F 35 ¼

3 þ 0 2 ¼

1
F 51 ¼ 0 þ 2 1 ¼ 1

0 þ 1 0 ¼

After figuring out the number of registers required for storing the intermediate results, the
architecture can be easily drawn. One adder and one multiplier are placed with two sets of 3:1
multiplexers with each functional unit. Now observing the folding set, connections are made from
the registers to the multiplier. For example, the adder first executes node 4. This node requires inputs
from node 2 and node 1. The values of F 24 and F 14 are 1 and 1, where node 2 is the multiplier node.
The connections to port 0 of the twomultiplexers at the input of the adder aremade by connecting the
output of one register after multiplier and one register after adder. Similarly, connections for all the
operations are made based on folding set and values of F ij .