Unfolding and Folding of Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 361

output signed [15:0] yn0, yn1); //Two outputs in Q1.15
parameter signed [15:0] a0=16 ' b0001_1101_0111_0000;
//0.23 in Q1.15
parameter signed [15:0] a1=16 ' b1100_1000_1111_0110;
//=0.43 in Q1.15
reg signed [15:0] mul0_reg[0:1];
reg signed [15:0] mul1_reg[0:1]; // Input sample delay line
reg signed [15:0] add1_reg[0:1];
reg signed [15:0] add0_reg[0:1];
reg signed [15:0] delay;
wire signed [15:0] add0_out[0:1], add1_out[0:1];
wire signed [31:0] mul0_out[0:1], mul1_out[0:1];
// Block Statements
always @( posedge clk or negedge rst_n)
if(!rst_n)
begin

add0_reg[0] <= 0;
add0_reg[1] <= 0;
mul0_reg[0] <= 0;
mul0_reg[1] <= 0;
mul1_reg[0] <= 0;
mul1_reg[1] <= 0;
add1_reg[0] <= 0;
add1_reg[1] <= 0;
delay <= 0;

end

else

begin

// Same number of algorithmic registers, retimed differently
add0_reg[0] <= add0_out[0];
add1_reg[0] <= add0_out[1];
mul0_reg[0] <= mul0_out[0][31:16];
mul1_reg[0] <= mul0_out[1][31:16];
add0_reg[1] <= add1_out[0];
add1_reg[1] <= add1_out[1];
mul0_reg[1] <= mul1_out[0][31:16];
mul1_reg[1] <= mul1_out[1][31:16];
delay <= yn1;

end

/* Unfolding by a factor of 2 makes two copies of the
combinational nodes /
assign add0_out[0]= xn0 + add1_reg[0];
assign mul0_out[0]= yn0 * a0;
assign mul0_out[1]= delay * a1;
assign add0_out[1]= mul0_reg[0]+mul1_reg[0];
assign yn0 = add0_reg[0];
assign add1_out[0]= xn1 + add1_reg[1];
assign mul1_out[0]= yn1 * a0;
assign mul1_out[1]= yn0 * a1;
assign add1_out[1]= mul0_reg[1]+mul1_reg[1];
assign yn1 = add0_reg[1];
endmodule