Unfolding and Folding of Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 359

output signed [15:0] yn); //Q1.15
parameter signed [15:0] a0=16 ' b0001_1101_0111_0000; //0.23 in Q1.15
parameter signed [15:0] a1=16 ' b1100_1000_1111_0110; //=0.43 in Q1.15
reg signed [15:0] add_reg[0:1] ;
reg signed [15:0] y_reg[0:3] ; // Input sample delay line
reg signed [15:0] delay;
wire signed [15:0] add_out[0:1];
wire signed [31:0] mul_out[0:1];
always @( posedge clk or negedge rst_n)
begin

if(!rst_n) // Reset all the registers in the feedback loop
begin

add_reg[0] <= 0;
add_reg[1] <= 0;
y_reg[0] <= 0;
y_reg[1] <= 0;
y_reg[2] <= 0;
y_reg[3] <= 0;
delay <= 0;

end
else
begin

// Assign values to registers
add_reg[0] <= add_out[0];
add_reg[1] <= add_reg[0];
y_reg[0] <= yn;
y_reg[1] <= y_reg[0];
y_reg[2] <= y_reg[1];
y_reg[3] <= y_reg[2];
delay <= y_reg[3];

end

end

// Implement combinational logic of two additions and
two multiplications
assign add_out[0] = xn + add_out[1];
assign mul_out[0]= y_reg[3] * a0;
assign mul_out[1]= delay * a1;
assign add_out[1] = mul_out[1][31:16]+mul_out[0][31:16];
assign yn = add_reg[1];
endmodule

/* Retime the algorithmic registers to reduce the critical
path while mapping the design on FPGAs
with DSP48-like blocks /
module IIRFilterRetime
(
input clk, rst_n,
input signed [15:0] xn, //Q1.15
output signed [15:0] yn); //Q1.15
parameter signed [15:0] a0 = 16 ' b0001_1101_0111_0000;
//0.23 in Q1.15