Unfolding and Folding of Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 356

always @( posedge clk)
begin
// Delay line for the input samples
xn_reg[0] <= xn1;
xn_reg[4] <= xn2;
xn_reg[1] <= xn_reg[4];
xn_reg[2] <= xn_reg[0];
xn_reg[3] <= xn_reg[1];
end
always @( posedge clk)
begin
// Registering the results of multipliers
mul_reg1[0] <= mul_out1[0];
mul_reg1[1] <= mul_out1[1];
mul_reg1[2] <= mul_out1[2];
mul_reg1[3] <= mul_out1[3];
mul_reg2[0] <= mul_out2[0];
mul_reg2[1] <= mul_out2[1];
mul_reg2[2] <= mul_out2[2];
mul_reg2[3] <= mul_out2[3];
end
always @( posedge clk)
begin
// Additions and registering the results
add_reg1[0] <= mul_reg1[0];
add_reg1[1] <= add_reg1[0]+mul_reg1[1];
add_reg1[2] <= add_reg1[1]+mul_reg1[2];
add_reg1[3] <= add_reg1[2]+mul_reg1[3];
add_reg2[0] <= mul_reg2[0];
add_reg2[1] <= add_reg2[0]+mul_reg2[1];
add_reg2[2] <= add_reg2[1]+mul_reg2[2];
add_reg2[3] <= add_reg2[2]+mul_reg2[3];
end
// Multiplications
assign mul_out1[0]= xn_reg[0] * h3;
assign mul_out1[1]= xn_reg[1] * h2;
assign mul_out1[2]= xn_reg[2] * h1;
assign mul_out1[3]= xn_reg[3] * h0;
assign mul_out2[0]= xn_reg[4] * h3;
assign mul_out2[1]= xn_reg[0] * h2;
assign mul_out2[2]= xn_reg[1] * h1;
assign mul_out2[3]= xn_reg[2] * h0;
// Assigning output in Q1.15 format
assign yn1 = add_reg1[3][31:16];
assign yn2 = add_reg2[3][31:16];
endmodule
8.4.6 Unfolding and Retiming in Feedback Designs
It has already been established that an unfolding transformation does not improve timing; rather, it
results in an increase in critical path delay and, for feedback designs, an increase in IPB by the