Unfolding and Folding of Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 352

ybf[n] = sum_n_0;
ybf[n-1] = sum_n_1;
ybf[n-2] = sum_n_2;
ybf[n-3] = sum_n_3;

}

}

The code processes N input samples in every iteration to compute N output samples in L iterations
of the innermost loop. The processing of the innermost loop requires the previous L 1 input

samples for computation of convolution summation. All the required input samples are stored in a
buffer xbf of size N 1. The management of the buffer is conveniently performed using

circular addressing, where every time N new input data values are written in the buffer replacing the
oldest N values. This arrangement always keeps the L

þ L

1 most recent previous values in the buffer.
Figure 8.6 shows mapping of the code listed above in hardware with four MAC and three delay
registers. This architecture only requires reading just one operand each from xbf and hbf
memories. These values are designated as x[m]andy[k]. At the start of every iteration the address
registers for xbf and hbf are initialized to m ¼ L þ 4 1andk ¼ 0, respectively. In every cycle
address, register m is decremented and k is incremented by 1. In L cycles the architecture computes
four output samples. The address m is then incremented for the next iteration of the algorithm.
Three cycles are initially required to fill the tap delay line. The architecture can be unfolded to
compute asmany output samples as required and still needs to read only onevalue fromeach buffer.
There is no trivial transformation or loop unrolling technique that automatically generates such an
optimized architecture. The designer's intellect and skills are usually required to develop an optimal
architecture.

8.4.4 Unfolding to Maximize Use of a Compression Tree
For hardware design of feedforward DFGs, effective architectural optionscanbeexploredusing
unfolding transformation. An unrolled design processes multiple input samples by using

x bf

0
1
2 h bf

x m x m-1 x m-3

x m-2

h 0
h 1

L-1

h k

N+L-1

m--

h L-1

k++

Figure 8.6 Hardware mapping of the code listed in the text