Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 293

0

0 0

1

0
1

0
1

0

0
1

h 0

x n

h 0

4

x n

+

…
.

add/sub

…
.

sub

sub

0

0
1

0
1

0

0
1

h 1

x n-1

…
.

+

h 1

2

x n-1

0

+

sub

…
.

+/-

2 -1

0

0 0

1

0
1

0

0
1

h 2

x n-2

…
. h 2

sub

x n-2

+

…
.

0

0
1

clk g

0
1

rst_n

h 3

0

0
1

clk g x n-3

sub clk g

h 3

rst_n

clk g

x n-3

clk G

clk g

clk G

clk G

en

CPA

clk G

(a) (b)

Figure 6.22 A LUT-less implementation of a DA-based FIR filter. (a) A parallel implementation for M ¼ K uses a 2:1 MUX, compression tree and a CPA.
(b) Reducing the output of the multiplexers using a CPA-based adder tree and one accumulator