Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 289

{15 ' b0, msb, 16 ' b0}) > > > 1; // add 1 at 16th bit location for 2 ' s
complement logic
always @ (posedge clk_g or negedge rst_n)
begin
if(!rst_n)
begin
// Initializing all the registers
xn_0 <= 0;
xn_1 <= 0;
xn_2 <= 0;
xn_3 <= 0;
acc <= 0;
end
else
begin
// Implementing daisy-chain for DA computation
xn_0 <= {xn_b, xn_0[15:1]};
xn_1 <= {xn_0[0], xn_1[15:1]};
xn_2 <= {xn_1[0], xn_2[15:1]};
xn_3 <= {xn_2[0], xn_3[15:1]};
// A single adder should be used instead, shift right to multiply by 2-i
if(&contr)
begin
yn <= sum;
acc <= 0;
end
else
acc <= sum;
end
end
endmodule
// Module uses multipliers to implement an FIR filter for verification of DA arch
module FIRfilter
(
input signed [15:0] x,
input clk_s, rst_n,
output reg signed [31:0] yn);
reg signed [15:0] xn_0, xn_1, xn_2, xn_3;
wire signed [31:0] yn_v, y1, y2, y3, y4;
// Coefficients of the filter
wire signed [15:0] h0 = 16 ' h0224;
wire signed [15:0] h1 = 16 ' h3DDC;
wire signed [15:0] h2 = 16 ' h3DDC;
wire signed [15:0] h3 = 16 ' h0224;
// Implementing filters using multiplication and addition operators
assign y1=h0*xn_0;
assign y2=h1*xn_1;
assign y3=h2*xn_2;
assign y4=h3*xn_3;