Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 272

a fuller-adder delay. This critical path is independent of filter length. A deeply pipelined filter
with one FA in the critical path is shown in Figure 6.10(b). A pipeline register is added after
every carry save adder. To maintain the data coherency in the pipeline architecture, registers are
added in all parallel paths of the architecture. Although a designer can easily place these registers
by ensuring that the coherent data is fed to each computational node in the design, a cut-set
transformation provides convenience in finding the location of all pipeline registers. This is covered
in Chapter 7.

6.6.4 Example: TDF Architecture
Consider the design of a TDF architecture for the filter in Section 6.6.2.
Solution: Amaximum of four non-zero digits in CSD representation of each coefficient are given
here:

00000101001001
00100010000000000
0100001001001
0010001000000000
00000101001001

For TDF we need to produce the following PPs for each multiplier M k :

M 4 ¼ x½n 2 5 x½n 2 7 þx½n 2 10 þx½n 2 13

M 3 ¼ x½n 2 2 x½n 2 6

M 2 ¼ x½n 2 1 x½n 2 6 x½n 2 9 x½n 2 12

M 1 ¼ x½n 2 2 x½n 2 6

M 0 ¼ x½n 2 5 x½n 2 7 þx½n 2 10 þx½n 2 13

Each PP is generating by hardwired shifting of x[n] by the respective non-zero CSD digit. These
PPs for each coefficient multiplication are reduced to two layers using a carry save adder. The result
from this reduction {c k , s k } is saved in registers {c kd , s kd }:

2 5 2 7 2 10 2 13 fc 4 ; s 4 g¼x½n x½n þx½n þx½n þ 0 þ 0

fc 3 ; s 3 g¼x½n 2 2 x½n 2 6

þ c 4 d þ s 4 d

fc 2 ; s 2 g¼x½n 2 1 x½n 2 6 x½n 2 9 x½n 2 12 þ c 3 d þ s 3 d

fc 1 ; s 1 g¼x½n 2 2 x½n 2 6 þ c 2 d þ s 2 d

fc 0 ; s 0 g¼x½n 2 5 x½n 2 7 þx½n 2 10 þx½n 2 13

þ c 1 d þ s 1 d

The values in c 0 and s 0 are either finally added using any CPA to compute the final result, or they
are forwarded in the partial form to the next stage of the algorithm. The CPA is not in the critical path
and can be deeply pipelined as desired.
An RTL design of the filter is shown in Figure 6.11 and the corresponding Verilog code is given
here.